The present invention relates to interface devices and more particularly to full duplex interface devices.
The introduction of various new computer/processor and communication technologies has increasingly led to a demand for communication interfaces to a variety of devices, such as electric home appliances, in addition to conventional computer devices. More particularly, one specific area where such technology has been applied is for communication of digital video media data between various devices within a user""s home. Examples of currently developed products which support such communications are set top boxes using the Moving Picture Expert Group-2 Transfer Stream (MPEG-2 TS) protocol, televisions, digital video cassette recorders (DVCR), digital video camcorders (DVC), controllers interfacing between computers and peripheral equipment and various data interface methods and devices.
One standard in particular which has been developed for providing cost effective interconnections between computer peripherals and consumer electronics is the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard for high performance serial buses. Various consumer type devices have been introduced which incorporate an IEEE 1394 compliant interface to support communications.
FIG. 1 is a block diagram which illustrates a conventional application using an IEEE 1394 compliant interface. As shown in FIG. 1, the IEEE 1394 interface unit 30 is connected to a source generator unit 10 and a display unit (or, alternatively, a storage unit) 20. The source generator unit 10 generates video signals in, for example, a transfer stream (TS) format. The generated signals are transmitted to the display unit 20 and further may be transmitted to a physical layer, such as an IEEE 1394 compliant cable, through the IEEE 1394 interface unit 30. The display unit 20 displays the video signals which are transmitted from the source generator unit 10, or, alternatively, may display signals received from another device (not shown) over the physical layer through the IEEE 1394 interface unit 30. The IEEE 1394 interface unit 30 in a first mode links signals provided from the source generator unit 10 to the physical layer. In a second mode (or direction) the IEEE 1394 interface unit 30 links signals provided from the physical layer to the display unit 20 or other devices on the source generator side of the IEEE 1394 interface unit 30.
Referring now to FIG. 2, a more detailed block diagram is provided illustrating the conventional IEEE 1394 interface unit 30 of FIG. 1. As shown in FIG. 2, the IEEE 1394 interface unit 30 includes an interface 31, a receiver 32, a cycle redundancy checker (CRC) 33, a transmitter 34, a receiving controller 35, a cycle monitor (CM) 36, a cycle timer (CT) 37, a transmitting controller 38 and buffers 39, 40. When signals are received from the physical layer, the received signals are provided to the receiver 32 through the interface 31. The CRC 33 checks for errors in the received signals so as to indicate a failure in receipt of a signal.
As known to those of skill in the art, both asynchronous and isochronous (ISO) signals are supported under the IEEE 1394 standard. Isochronous signals, such as video signals, are provided to the buffer 39 through the receiving controller 35. The asynchronous signals are provided to the buffer 40 through the receiving controller 35. Furthermore, the receiving controller 35 provides the signals from the receiver 32 to the cycle monitor 36. In turn, the cycle monitor 36 monitors the timing of the received signals.
The buffer 39 is generally provided as a first-in first-out (FIFO) memory unit which temporarily stores received and transmitted ISO signals. During operations related to receiving signals from the physical layer, the buffer 39 functions as an isochronous receiving FIFO (IRF) memory unit. During operations related to transmitting signals onto the physical layer, the buffer 39 functions as an isochronous transmitting FIFO (ITF) memory unit. As noted previously with reference to FIG. 1, when the received ISO signals are read back out of the buffer 39, they are generally transmitted to the display unit 20.
The buffer 40 may also be provided by FIFO memory units which operate to temporarily store received and transmitted asynchronous signals. Accordingly, during operations related to receipt of asynchronous signals from the physical layer, the buffer 40 functions as an asynchronous receiving FIFO (ARF) memory unit and, during operations related to transmission of signals onto the physical layer, the buffer 40 functions as an asynchronous transmitting FIFO (ATF) memory unit. Generally, received asynchronous signals which are passed through the buffer 40 are transmitted to a controller device which controls operations of the system including the source generator unit 10 and display unit 20 of FIG. 1. While not illustrated in FIG. 1, it is to be understood that the controller device receiving such asynchronous signals can be a variety of devices known to those of ordinary skill in the art.
As noted above, ISO signals, such as video signals generated by the source generator unit 10, are temporarily stored in the buffer 39 before transmission over the physical layer. Accordingly, as ISO signals flow both to and from the source generator unit 10, a bidirectional port is used to interface the source generator unit 10 and display unit 20 to the buffer 39 so that ISO signals may be both transmitted and received to/from the source generator unit 10 and the display unit 20, respectively. Accordingly, the ISO signals may be bidirectionally transmitted and received through the buffer 39. However, in the illustrated conventional IEEE 1394 interface unit 30, the ISO signals cannot be bidirectionally transmitted and received concurrently as there is no support provided for such full duplex operations.
It is further to be understood that, during operations, the circuit of FIG. 2 passes ISO signals from the source generator unit 10 through the buffer 39 to the transmitter 34 through the transmitting controller 38. In turn, the transmitting controller 38 tunes the synchronizing timing of the ISO transmitted signals responsive to timing information provided from the cycle timer 37. The transmitting controller 38 then provides the tuned signals to the transmitter 34. Finally, the timing-tuned ISO signals output from the transmitter 34 are combined with CRC-signals for use in error checking which are provided by the CRC 33 before transmission of the ISO signals to the physical layer through the interface 31.
The half duplex communication operations of the conventional IEEE 1394 interface unit 30 are further illustrated in FIGS. 3a and 3b. As shown in FIG. 3a, video signals generated in the source generator unit 10 may be transmitted to the display unit 20 and concurrently transmitted to other devices, such as other home appliances, through the IEEE 1394 interface unit 30 and over the physical layer. As shown in FIG. 3b, video signals provided from an external device, such as a home appliance, and provided over the physical layer are transmitted to the display unit 20 through the IEEE 1394 interface unit 30. However, as the illustrated conventional IEEE 1394 interface unit 30 has only a single, bidirectional port, it is generally not possible to transmit signals generated in the source generator unit 10 to the physical layer through the IEEE 1394 interface unit 30 while concurrently transmitting the signals provided from the physical layer to the display unit 20. In other words, while half duplex communication is supported, full duplex communication is not supported.
It is, therefore, an object of the present invention to provide an interface for a high performance serial bus which may allow full duplex communications.
In order to provide for the foregoing objective, a full duplex interface apparatus for a high performance serial bus is provided. More particularly, an IEEE 1394 interface apparatus is provided which includes a port switch having two ports coupled to a source generator device and a display device and separately receiving and buffering received signal packet data streams from the physical layer and transmit signal packet data streams for transmission over the physical layer. Accordingly, by coupling the source generator unit which generates signals for transmission over the physical layer through a first port of the port switch and the display unit to a second port of the port switch, ISO signals such as video signals may be received from the physical layer and provided to the display unit at the same time as ISO signals are being transmitted from the source generator unit to the physical layer through the port switch.
In one embodiment of the present invention, a full duplex interface apparatus for a higher performance serial bus, such as an IEEE 1394 protocol serial bus, is provided. The interface includes an interface circuit having a transmit signal output coupled to the high performance serial bus and a receive signal input coupled to the high performance serial bus. The interface circuit is configured to receive isochronous signals from the high performance serial bus on the receive signal input and to transmit isochronous signals to the high performance serial bus on the transmit signal output. A port switch is coupled to the interface circuit which has a first port and a second port, the first port and the second port being coupled to a source generator unit. The port switch is configured to support full duplex communication of isochronous signals between the high performance serial bus and the source generator through the first port and the second port.
In one embodiment, the isochronous signals are video signals. The isochronous signals may be provided in a packet which includes a time stamp indicating location information for the packet relative to other packets communicated over the high performance serial bus. In this embodiment, the interface circuit includes a packet reconstruction circuit configured to read the time stamp from a received packet and determine a desired location for the received packet and a time stamp insertion circuit configured to add a time stamp to a transmit packet indicating location information for the transmit packet relative to other packets generated by the source generator. In a further embodiment, the interface circuit further includes a receive buffer that stores isochronous signals received from the high performance serial bus and a transmit buffer separate from the receive buffer that stores isochronous signals received from the source generator.
In a further embodiment of the present invention, the first port is a bidirectional port and the second port is a unidirectional port supporting communication of isochronous signals from the source generator to the high performance serial bus. The first port supports communication of isochronous signals from the high performance serial bus to the source generator during full duplex operations of the apparatus. The interface circuit in a further embodiment includes an IEEE 1394 compliant connector and the transmit signal output and the receive signal input are coupled to the high performance serial bus through the IEEE 1394 compliant connector.
In a further embodiment of the present invention, the port switch includes a first logic AND gate having a first input coupled to the receive signal input and a second input coupled to a first enable signal. A first transmit gate is coupled to an output of the first logic AND gate which is responsive to a second enable signal, the first transmit gate providing a high impedence at an output of the first transmit gate when the second enable signal is deactivated, the output of the first transmit gate being coupled to the first port. A second logic AND gate having a first input coupled to the first port and a second input coupled to the first enable signal and an output coupled to the transmit signal output is included. The receive signal input is coupled to the second port.
In another embodiment, a buffer is provided having an input coupled to the first port. In addition, a multiplexer having a first input port coupled to the receive signal input and a second input coupled to an output of the buffer is provided as well as a second transmit gate having an input coupled to an output of the multiplexer and being responsive to a third enable signal and having an output coupled to the second port. The first input of the second logic AND gate is coupled to an output of the buffer.
In yet another embodiment, an asynchronous signal interface circuit is provided which is coupled to the high performance serial bus and configured to receive asynchronous signals from the high performance serial bus. The asynchronous signal interface circuit may include an interface having an output coupled to a controller associated with the source generator, a receive buffer coupled between the high performance serial bus and a first input of the interface and a transmit buffer coupled between the high performance serial bus and a second input of the interface.